When a high number of electric pulses are to be counted, particularly when measuring time intervals, it is necessary to use a counter circuit having several stages, or elementary counters.
A period or length of time between two events may be determined by starting to count clock pulses on the arrival of a command corresponding to the first event, and by ending counting on the arrival of a second command corresponding to the second event. The difference between the starting and ending counts is equal to the number of pulses received between the two commands, and is representative of the time interval to be measured. In this mode of operation it is generally desirable to start counting with all the stages of the counter circuit at zero, whereby the count at the end of counting is directly equal to the number sought.
There is a second mode of counting which uses a counter that is running continuously, and in which instantaneous states of the counter are read at the start and at the end of the period to be measured.
In such a system, the counter is continuously driven by a clock signal. On receiving a first command corresponding to a first event, the state of the counter is read using a register with stages connected to respective stages of the counter. The register is read enabled for a short period to load the instantaneous state of the counter therein. The same register, or a second register connected to the stages of the counter in like manner to the first, is subsequently read enabled in response to an end of counting command corresponding to a second event, whereby the instantaneous state of the counter at the moment of arrival of the second command is loaded into the register. The time interval between the first and second events can then easily be determined from the information stored in the first and second registers.
For this second mode to give correct results, it is essential that each counter stage is in a condition which genuinely corresponds to the number of clock pulses actually counted at the instants when the start count and the end count commands arrive.
While this condition is satisfied in counter circuits wherein all the successive stages or elementary counters that constitute the circuit are connected to receive clock pulses simultaneously (commonly called "synchronous" counters), the same is not true when the stages are connected one after the other in such a manner that the n-th counter stage is driven by pulses from the immediately preceding (n-1)th stage. Each stage takes a finite time to operate, which although short, is nonetheless real, causing the higher stages of such counters with series connected stages (commonly called "asynchronous" or "ripple" counters) to switch only after a considerable length of time has elapsed since the pulse which caused the corresponding switch in the lowest order stage.
When very high frequency clock pulses are used, it can happen that the higher order stages of the counter have not finished switching in response to a clock pulse at the time the counter is being read. Consequently, it is not impossible that the state in each of the stages of such a counter circuit does not correspond to the number of clock pulses actually received at the input to the counter, at the moment a command arrives to indicate the start or end of counting.
In applications that require continuous counting with the counter being read on the fly, this has resulted in the use of ripple counters being restricted to cases where the pulses to be counted are at not too high a frequency. When this is not the case, synchronous counters are used, i.e. counters whose several stages are driven simultaneously by the clock pulses. Such counter circuits are expensive and consume a relatively high quantity of electrical power.
The object of the present invention is to provide a counter which is particularly suited to counting high frequency pulses.